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| www..com NT75451 132 X 65 RAM-Map STN LCD Controller/Driver V1.0 NT75451 www..com Revision History................................................................................................................................. 3 Features.............................................................................................................................................. 4 General Description........................................................................................................................... 4 Pad Configuration.............................................................................................................................. 5 Block Diagram.................................................................................................................................... 6 Pad Descriptions................................................................................................................................ 7 Functional Descriptions .................................................................................................................. 12 Commands ....................................................................................................................................... 26 Command Description..................................................................................................................... 42 Absolute Maximum Rating .............................................................................................................. 45 Electrical Characteristics .............................................................................................................. 455 Microprocessor Interface (for reference only) ............................................................................... 54 Bonding Diagram ............................................................................................................................. 60 Package Information...................................................................................................................... 655 Application Notice ..............................................................................................................................66 ITO Layout Notice .............................................................................................................................. 67 2008/12/30 2 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Revision History NT75451 Specification Revision History Prepared Version 0.1 Original Modify ITO layout notice of ITO resistance on page 71. 0.2 Modify Serial Interface Timing on page 55, 56 Remove OTP Function Release Ethen Shai Eric Lai Dennis Kuo March 2008 Content by Ethen Shai by by Dennis Kuo November 2007 Checked Approved Date www..com 0.3 1.0 Ethen Shai Ethen Shai K Y Chen K Y Chen Dennis Kuo Dennis Kuo May 2008 Dec.2008 2008/12/30 3 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Features www..com 132 x 65-dot graphics display LCD controller/driver for black/white STN LCD RAM capacity: 132 x 65 = 8,580 bits 8-bit parallel bus interface for both 8080 and 6800 series, 4-wire Serial Peripheral Interface (SPI) Direct RAM data display using the display data RAM. When RAM data bit is 0, it is not displayed. When RAM data bit is 1, it is displayed. (At normal display) Many command functions: Read/Write display data, display ON/OFF, Normal/Reverse display, page address set, display start line set, LCD bias set, electronic contrast controls, V0 voltage regulation internal resistor ratio set, read modify write, segment driver direction select, power save. Other command functions: Partial display, partial start line set, N-Line inversion. Power supply voltage: - VDD = 1.8 ~ 3.6 V (Digital, Interface Power Input Range) - VDD2 = 2.6 ~ 3.6 V (Pump Power Input Range) - VDD3 = 2.4 ~ 3.6 V (Analog Power Input Range) - VLCD(V0-VSS2) = 3.85 ~ 13.44 V (When use internal power circuit) 3X / 4X / 5X on chip DC-DC converter On chip LCD driving voltage generator or external power supply selectable 64-step contrast adjuster and on chip voltage follower On chip oscillation and hardware reset General Description The NT75451 is a single-chip LCD driver for dot-matrix liquid crystal displays, which is directly connectable to a microcomputer bus. It accepts 8-bit parallel or serial display data directly sent from a microcomputer and stores it in an on-chip display RAM. It generates an LCD drive signal independent of the microprocessor clock. The set of the on-chip display RAM of 65 x 132 bits and a one-to-one correspondence between LCD panel pixel dots and on-chip RAM bits permits implementation of displays with a high degree of freedom. The NT75451 contain 65 common output circuits and 132 segment output circuits, so that a single chip of NT75451 can make maximum 65 x 132 or 49 x 132 or 33 x 132 dots display with the pad option (DUTY1, DUTY0). No external operation clock is required for RAM read/write operations. Accordingly, this driver can be operated with a minimum current consumption and its on-board low-current-consumption liquid crystal power supply can implement a high-performance handy display system with minimum current consumption and the smallest LSI configuration. 2008/12/30 4 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Pad Configuration www..com 2008/12/30 5 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Block Diagram www..com SEG 0 VDD , VDD3 VSS,VSS3 (V0) (V1) (V2) (V3) (V4) VSS VSS2,VSS3 SEG131 COM0 COM63 COMS Segment driver Common driver COM S Shift register V0 V1 V2 V3 V4 Voltage Follower Display data latch VDD2 VSS2 I/O buffer circuit 132*65-dot dispaly data RAM Output status selector circuit Column address decoder Page address register 8-bit column address counter Display timing generator circuit Line counter Booster Line address decoder Voltage Initial display line register DUTY 0 DUTY 1 CL FRS FR Bus holder Command decoder Bus holder Oscillator CLS Microprocessor interface I/O buffer /CS1 CS2 A0 /RD (E) / WR C86 (R/W) P/S / RES D7 (SI) D6 ( SCL) D5 D4 D3 D2 D1 D0 2008/12/30 6 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Pad Descriptions Power Supply Pad No. Designati on VDD I/O Description Power supply input. These pads must be connected to each other. These are the power supply pads for the step-up voltage circuit for the LCD. These pads must be connected to each other. Power supply input. These pads must be connected to each other. Power supply output for pad option Ground. These pads must be connected to each other. Ground. These pads must be connected to each other. Ground. These pads must be connected to each other. www..com 26~28 Supply 32~35 VDD2 Supply 29~31 14,54 36~38 42~45 39~41 7,24,57 3~4 6 VDD3 VDD_OPT VSS VSS2 VSS3 VSS_OPT OTP_PWR CP Supply O Supply Supply Supply O Supply I Ground output for pad option. Test pin, not accessible to user, must be left open. H/W Select pump times 4x or 5x. (L=4x & H=5x). After H/W reset, the booster stage will be the setting value. 2008/12/30 7 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com LCD Power Supply Pad No. 50~53 Designation VLCD (V0) I/O Description LCD driver supplies voltages. The voltage determined by the LCD cell is impedance-converted by a resistive driver or an operation amplifier for application. Voltages should be according to the following relationship: V0 V1 V2 V3 V4 VSS2 When the on-chip operating power circuit is on, the following voltages are supplied to V1 to V4 by the on-chip power circuit. Voltage selection is performed by the LCD Bias Set command. I/O LCD bias 1/4 bias 1/5 bias 48 V3 1/6 bias 1/7 bias 49 V4 1/8 bias 1/9 bias V1 3/4V0 4/5V0 5/6V0 6/7V0 7/8V0 8/9V0 V2 2/4V0 3/5V0 4/6V0 5/7V0 6/8V0 7/9V0 V3 2/4V0 2/5V0 2/6V0 2/7V0 2/8V0 2/9V0 V4 1/4V0 1/5V0 1/6V0 1/7V0 1/8V0 1/9V0 46 V1 47 V2 Configuration Pad Pad No. Designation I/O Description Select the maximum LCD driver duty DUTY1 DUTY0 LCD driver duty 0 0 1/33 0 1 1/49 1 * 1/65 23 25 DUTY0 DUTY1 I 2008/12/30 8 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 System Bus Connection Pad No. 15 16 17 18 19 20 21 22 Designation D0 D1 D2 D3 D4 D5 D6 (SCL) D7 (SI) I/O Description This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S="L"), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). When the serial interface is selected, fix D0~D5 pads to VSS level. When the chip select is inactive, D0 to D7 are set to high impedance. This is connected to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = "H": Indicate that D0 to D7 are display data A0 = "L": Indicates that D0 to D7 are control data When /RES is set to "L", the settings are initialized. The reset operation is performed by the /RES signal level This is the chip select signal. When /CS1="L" and CS2="H", then the chip select becomes active, and data/command I/O is enabled. When connected to an 8080 MPU, it is active LOW. This pad is connected to the /RD signal of the 8080MPU, and the NT75451 data bus is in an output status when this signal is "L". When connected to a 6800 Series MPU, this is active HIGH. This is used as an enable clock input of the 6800 series MPU When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU /WR signal. The signals on the data bus are latched at the rising edge of the /WR signal. When connected to a 6800 Series MPU, this is the read/write control signal input terminal. When R/W = "H": Read When R/W = "L": Write This is the MPU interface switch terminal C86 = "H": 6800 Series MPU interface C86 = "L": 8080 Series MPU interface www..com I/O 11 A0 I 10 8 9 /RES /CS1 CS2 I I 13 /RD (E) I 12 /WR (R/W) I 56 C86 I 2008/12/30 9 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 System Bus Connection (continuous) Pad No. Designation I/O Description This is the parallel data input/serial data input switch terminal P/S = "H": Parallel data input P/S = "L": Serial data input The following applies depending on the P/S status: P/S Data/Command 58 P/S I "H" "L" A0 A0 Data D0 to D7 SI (D7) Read/Write Serial Clock /RD, /WR Write only SCL (D6) www..com When P/S = "L", fix D0~D5 pads to VSS level. /RD (E) and /WR (R/W) are fixed to "L". With serial data input, RAM display data reading is not supported. Terminal to select whether enable or disable the display clock internal oscillator circuit. CLS = "H": Internal oscillator circuit for display is enabled CLS = "L": Use external oscillator circuit for display (requires external input) When CLS = "L", input the display clock through the CL pad. This is the display clock output/input terminal. When CLS = "H" : the CL will be output terminal; and when CLS="L" : the display requires external input clock. This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON, and is used in conjunction with the FR terminal. This is liquid crystal alternating current signal output terminal. 55 CLS I 5 CL I/O 1 2 FRS FR O O 2008/12/30 10 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Liquid Crystal Drive Pads Pad No. 92~223 59~90 224~255 Designation SEG0 - 131 COM31 - 0 COM32 - 63 I/O O O Description Segment signal output for LCD display. Common signal output for LCD display. When in master/slave mode, the same signal is output by both master and slave These are the COM output terminals for the indicator. Both terminals output the same signal. Do not connect these terminals if they are not used. When in master/slave mode, the same signal is output by both master and slave. www..com 91,256 COMS O 2008/12/30 11 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Functional Descriptions Microprocessor Interface Interface Type Selection The NT75451 can transfer data via 8-bit bi-directional data bus (D7 to D0) or via serial data input (SI). When high or low is selected for the parity of P/S pad either 8-bit parallel data input or serial data input can be selected as shown in Table 1. When serial data input is selected, the RAM data cannot be read out. Table 1 P/S H L Type Parallel Input Serial Input /CS1 /CS1 /CS1 CS2 CS2 CS2 A0 A0 A0 /RD /RD /WR /WR C86 C86 D7 D7 SI D6 D6 SCL D0 to D5 D0 to D5 www..com "-" Must always be low Parallel Interface When the NT75451 selects parallel input (P/S = high), the 8080 series microprocessor or 6800 series microprocessor can be selected by causing the C86 pad to go high or low as shown in Table 2. Table 2 C86 H L Type 6800 microprocessor bus 8080 microprocessor bus /CS1 /CS1 /CS1 CS2 CS2 CS2 A0 A0 A0 /RD E /RD /WR R/W /WR D0 to D7 D0 to D7 D0 to D7 Data Bus Signals The NT75451 identifies the data bus signal according to A0, E, R/W (/RD, /WR) signals. Table 3 Common 6800 processor A0 1 1 0 0 (R/W) 1 0 1 0 8080 processor /RD 0 1 0 1 /WR 1 0 1 0 Reads display data Writes display data Reads status Writes control data in internal register. (Command) Function 2008/12/30 12 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com Serial Interface When the serial interface has been selected (P/S = "L"), then when the chip is in active state (/CS1 = "L" and CS2 = "H"), the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits of parallel data in the rising edge of eighth serial clock for processing. The A0 input is used to determine whether or not the serial data input is display data, and when A0 = "L" then the data is command data. The A0 input is read and used for detection of every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is the serial interface signal chart. Figure 1 CS /CS1 = "L" and CS2 = "H" SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 SCL 1 A0 Note: 1. When the chip is not active, the shift registers and the counters are reset to their initial states. 2. Reading is not possible while in serial interface mode. 3. Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that the operation can be rechecked on the actual equipment. Chip Select Inputs The NT75451 has two chip-select pads. /CS1 and CS2 can interface to a microprocessor when /CS1 is low and CS2 is high. When these pads are set to any other combination. D0 to D7 are high impedance and A0, E and R/W inputs are disabled. When serial input interface is selected, the shift register and counter are reset. Access to Display Data RAM and Internal Registers The NT75451 can perform a series of pipeline processing between LSI's using the bus holder of the internal data bus in order to match the operating frequency of display RAM and internal registers with the microprocessor. For example, the microprocessor reads data from display RAM in the first read (dummy) cycle, stores it in the bus holder, and outputs it onto the system bus in the next data read cycle. Also, the microprocessor temporarily stores display data in the bus holder, and stores it in display RAM until the next data write cycle starts. When viewed from the microprocessor, the NT75451 access speed greatly depends on the cycle time rather than access time to the display RAM (tACC). This view shows that the data transfer speed to / from the microprocessor can increase. If the cycle time is inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the immediately following read instruction. The address data is output during the second data read. A single dummy read must be inserted after address setup and after the write cycle (refer to Figure 2). 2008/12/30 13 Ver 1.0 2 3 4 5 6 7 8 9 10 11 12 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Figure 2 A0 MPU E R/W www..com DATA Address preset Read signal Internal timing Column address N N n n+1 Preset N Incremented N+1 N+2 BUS holder Set address n N Dummy read n n+1 n+2 Data Read address n+1 Data Read address n Busy Flag When the busy flag is "1" it indicates that the NT75451 chip is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pad with the read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. Display Data RAM The display data RAM is RAM that stores the dot data for the display. It has a 65 (8 page * 8 bit+1)*132 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display common direction, and there are few constraints at the time of display data transfer when multiple NT75451 chips are used, thus display structures can be created easily with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during the liquid crystal display, it will not cause adverse effects on the display (such as flickering). Figure 3 D0 D1 D2 D3 D4 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 COM0 COM1 COM2 COM3 COM4 Display on LCD 14 Ver 1.0 Display data RAM 2008/12/30 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com The Page Address Circuit As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address8 (D3, D2, D1, D0 = 1, 0, 0, 0,) is the page for the RAM region used; only display data D0 is used. The Column Address As shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read / write command. This allows the MPU display data to be accessed continuously. Moreover, the incrimination of column addresses stops with 83H, because the column address is independent of the page address. Thus, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to specify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. Table 4 SEG Output ADC "0" (ADC) "1" SEG0 0 (H) Column Address 83 (H) Column Address SEG131 83 (H) 0 (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified. This is the COM0 output when the common output mode is normal and the COM63 output for NT75451, when the common output mode is reversed. The display area is a 65-line area for the NT75451 from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The internal oscillator circuit is only enabled when CLS = "H". When CLS = "L" the internal oscillation stops, and the input display clock is through the CL terminal. 2008/12/30 15 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com Figure 4. Relationship between display data RAM and address. (if initial display line is 1DH) Line Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Page Address Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D0=0 00 01 02 COM output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS D3, D2, D1, D0 0, 0, 0, 0 Page0 0, 0, 0, 1 Page1 0, 0, 1, 0 Page2 0, 0, 1, 1 Page3 Start 0, 1, 0, 0 Page4 0, 1, 0, 1 Page5 0, 1, 1, 0 Page6 0, 1, 1, 1 Page7 1, 0, 0, 0 Column address Page8 81 02 SEG129 82 01 SEG130 83 SEG131 00 ADC D0=1 83 SEG0 82 SEG1 2008/12/30 SEG2 LCD OUT 81 16 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of access to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive waveform using a 2 frames alternating current drive method, as shown in Figure 5, for the liquid crystal drive circuit. Figure 5 64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 www..com CL FR COM0 V0 V1 V4 VSS V0 V1 COM1 V4 VSS RAM data V0 SEGn V2 V3 VSS 2008/12/30 17 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Table 5 shows the relationship between oscillation frequency and frame frequency. fOSC www..com can be selected as 31.4K or 26.3KHz by using Oscilliation Frequency Select command. Table 5 Duty 1/65 Item On-chip oscillator is used fOSC/6 fCL fFR fCL/(2 x 65) fCL/(2 x 65) fCL/(2 x 49) fCL/(2 x 49) fCL/(2 x 33) fCL/(2 x 33) fCL/(2 x 17) fCL/(2 x 17) fCL/(2 x 9) fCL/(2 x 9) On-chip oscillator is not used External input fCL 1/49 On-chip oscillator is used fOSC/8 On-chip oscillator is not used External input fCL 1/33 On-chip oscillator is used fOSC/12 On-chip oscillator is not used External input fCL 1/17 On-chip oscillator is used fOSC/22 On-chip oscillator is not used External input fCL 1/9 On-chip oscillator is used fOSC/44 On-chip oscillator is not used External input fCL Common Output Control Circuit This circuit controls the relationship between the number of common output and specified duty ratio. Common output mode select instruction specifies the scanning direction of the common output pads. Table 6 Common output pads Duty Status COM [0-15] COM [16-23] COM [24-26] COM [27-36] NC NC NC NC COM[0-63] COM[63-0] COM [37-39] COM [40-47] COM [48-63] COM[16-31] COM[15-0] COM[24-47] COM[23-0] COMS COMS 1/33 Normal COM[0-15] Reverse COM[31-16] Normal Reverse Normal Reverse COM[0-23] COM[47-24] 1/49 COMS 1/65 COMS The combination of the display data, the COM scanning signals, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows example of the SEG and COM output waveform. Configuration Setting The NT75451 has two optional configurations, configured by DUTY0, DUTY1. DUTY1, DUTY0 1, 0 or 1, 1 0, 1 0, 0 2008/12/30 Common 65 49 33 Segment 132 132 132 V1 V2 V3 V4 8/9V0, 6/7V0 7/9V0, 5/7V0 2/9V0, 2/7 V0 1/9V0, 1/7V0 7/8V0, 5/6V0 6/8V0, 4/6V0 2/8V0, 2/6 V0 1/8V0, 1/6V0 5/6V0, 4/5V0 4/6V0, 3/5V0 2/6 V0, 2/5V0 1/6V0, 1/5V0 18 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Figure 6 www..com FR VDD VSS V0 V1 V2 V3 V4 VSS2 V0 V1 V2 V3 V4 VSS2 V0 V1 V2 V3 V4 VSS2 V0 V1 V2 V3 V4 VSS2 V0 V1 V2 V3 V4 VSS2 V0 V1 V2 V3 V4 VSS2 V0 V1 V2 V3 V4 VSS2 -V4 -V3 -V2 -V1 -V0 V0 V1 V2 V3 V4 VSS2 -V4 -V3 -V2 -V1 -V0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM2 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG1 SEG0 COM1 COM0 SEG2 COM0 - SEG0 COM0 - SEG1 2008/12/30 19 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com The Power Supply Circuit The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the booster circuits, and the voltage follower circuits ON or OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 2-bit data control functions, and Table 8 shows reference combinations. Table 7 Item D2 Voltage Booster (V/B) circuit control bit D0 Voltage follower (V/F) circuit control bit Status "1" ON ON "0" OFF OFF Table 8 V/B D2 D0 Circuit V/F circuit External voltage input Step-up voltage system terminal Used Open Open Use Settings Only the internal power supply is used Only the V/F circuit is used Only the external power supply is used 1 0 0 1 1 0 ON OFF OFF ON ON OFF VDD2 V0, VDD2 V0 to V4 *While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. 2008/12/30 20 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com The Internal Pumping Voltage Using the step-up voltage circuits within the NT75451 chips it is possible to product 5X, 4X, 3X step-ups of the VDD2-VSS2 voltage levels by command (Ref 29. DC/DC Multiple Set). The internal pumping voltage, please keep the relationship: Pumping Times * VDD2 > VLCD + Temperature Compensation Voltage. Figure 7 5 X VDD2 4 X VDD2 VSS 2 = 0V VSS 2 = 0V 5x step-up voltage 4x step-up voltage 3 X VDD2 VSS 2 = 0V 3x step-up voltage The Voltage Regulator Circuit The function of the internal voltage regulator circuits is to determine liquid crystal operating voltage, V0. Because the NT75451 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V0 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Otherwise, NT75451 has temperature coefficient is -0.05%/C. 2008/12/30 21 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com When the V0 Voltage Regulator Internal Resistors Are Used Through the use of the V0 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V0 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V0 voltage can be calculated using equation A-1 over the range where V0 < Pumping Times x VDD2. V0 (1 Rb Rb 63 ) VEV (1 ) (1 ) VREG Ra Ra 162 (Equation A-1) VREG is the IC internal fixed voltage supply, and its voltage at Ta = 25C is as shown in Table 9. Table 9 Equipment Type Internal Power Supply Temp. coefficient -0.05 Units %/C VREG 1.4 is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for depending on the electronic volume register settings. Rb/Ra is the V0 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V0 voltage regulator internal resistor ratio set command. The (1+Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V0 voltage regulator internal resistor ratio register. Table 10 D5 0 0 0 1 1 1 D4 0 0 0 0 1 1 D3 0 0 0 : 0 : 1 1 1 1 1 1 0 0 D2 0 0 0 D1 0 0 1 D0 0 1 0 : 0 : 0 1 0 1 2 : 32 : 62 63 V0 Minimum : : : (default) : : Maximum 2008/12/30 22 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com V0 voltage regulator internal resistance ratio register value and (1+ Rb/Ra) ratio (Reference value) Table 11 Register D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Equipment Type by Temp. Cofficient [Units:%/C] -0.05 4.50 5.25 6.00 6.75 7.50 (default) 8.25 9.00 9.60 The V0 voltage as a function of the V0 voltage regulator internal resistor ratio register and the electronic volumn register. Note: When selecting external Rb/Ra resistors, Ra+Rb shoud be greater than 1.5M. Figure 8. The Contrast Curve of V0 Voltage with internal resistors 16 14 12 V0 (V) 10 8 6 4 2 0 0 10 20 30 40 50 60 Electronic Volume (0,0,0) 4.5 (0,0,1) 5.25 (0,1,0) 6 (0,1,1) 6.75 (1,0,0) 7.5 (1,0,1) 8.25 (1,1,0) 9 (1,1,1) 9.6 2008/12/30 23 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com Setup example: When selecting Ta=25C and V0=7V for a NT75451 model on which the temperture compemsation is internal, using the equation A-1, the following setup is enable. Table 12 Contents For V0 voltage regulator Electronic Volume 1 0 Register D5 D4 D3 D2 D1 D0 0 0 1 1 0 0 1 When the V0 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. The Liquid Crystal Voltage Generator Circuit The V0 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3, and V4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for NT75451 can be selected when the duty is 1/65. (Other applications, pleasse refer the LCD Bias set). 2008/12/30 24 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com Reset Circuit When the /RES input falls to "L", these LSIs reenter their default state. The default settings are shown below: 1. Display OFF 2. Normal display 3. ADC select: Normal display (ADC command D0 = "L") 4. Power control register (D2, D1, D0) = (0, *, 0,) 5. Register data clear in serial interface 6. LCD power supply bias ratio 1/9 (1/65 duty), 1/8 (1/49 duty), 1/6 (1/33 duty) 7. DC/DC Multiple Set (CP=L, 4X; CP=H,5x) 8. Read modify write OFF 9. Static indicator: OFF Static indicator register: (D1, D2) = (0, 0) 10. Display start line register set at first line 11. Column address counter set at address 0 12. Page address register set at page 0 13. Common output status normal 14. V0 voltage regulator internal power supply ratio set mode clear: V0 voltage regulator internal resistor ratio register: (D2, D1, D0) = (1, 0, 0) 15. Electronic volume register set mode clear Electronic volume register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0,) 16. Test mode clear 17. Oscillation frequency 31.4 KHz 18. Normal display mode and frame inversion status (partial display and N-Line inversion release) 19. N-Line inversion register: (D4, D3, D2, D1, D0) = (0, 1, 1, 0, 0), 13-Line inversion 20. Partial start line register: (D5, D4, D3, D2, D1, D0) = (0, 0, 0, 0, 0, 0), the first line 21. Output condition of COM, SEG COM: VSS SEG: VSS On the other hand, when the reset command is used, only default settings 8 to 16 above are put into effect. The MPU interface (Reference Example)", the /RES terminal is connected to the MPU reset terminal, making the chip reinitialize simultaneously with the MPU. At the time of power up, it is necessary to reinitialize using the /RES terminal. Moreover, when the control signal from the MPU is in a high impedance state, there may be an overcurrent condition; therefore, take measures to prevent the input terminal from entering a high impedance state. In the NT75451, if the internal liquid crystal power supply circuit is not used, user has to supply the external liquid crystal power after the procedure of RESET has been finished (please refer to the timing chart of Reset). During the period of external liquid crystal power supply being supplied, the /RES must be kept "H". Even though the oscillator circuit operates while the /RES terminal is "L," the display timing generator circuit is stopped. 2008/12/30 25 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Commands www..com The NT75451 uses a combination of A0, /RD (E) and /WR (R/W) signals to identify data bus signals. As the chip analyzes and executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its busy check is usually not required. The 8080 series microprocessor interface enters a read status when a low pulse is input to the /RD pad and a write status when a low pulse is input to the /WR pad. The 6800 series microprocessor interface enters a read status when a high pulse is input to the R/W pad and a write status when a low pulse is input to this pad. When a high pulse is input to the E pad, the command is activated. (For timing, see AC Characteristics.). Accordingly, in the command explanation and command table, /RD (E) becomes 1(high) when the 6800 series microprocessor interface reads status of display data. This is the only different point from the 8080 series microprocessor interface. Taking the 8080 series microprocessor interface as an example, commands are explained below. When the serial interface is selected, input data starting from D7 in sequence. 1. Display ON/OFF Alternatively turns the display on and off. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 1 0 1 1 1 1 0 Hex AFh AEh Setting Display ON Display OFF When the display OFF command is executed when in the display all points ON mode, power save mode is entered. See the section on the power saver for details. 2. Display Start Line Set Specifies line address (refer to Figure 6) to determine the initial display line, or COM0. The RAM display data becomes the top line of LCD screen. The higher number of lines in ascending order, corresponding to the duty cycle follows it. When this command changes the line address, smooth scrolling or a page change takes place. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 0 1 A5 A4 A3 A2 A1 A0 Hex 40h to 7Fh A5 0 0 0 1 1 A4 0 0 0 1 1 A3 0 0 0 : 1 1 A2 0 0 0 1 1 A1 0 0 1 1 1 A0 0 1 0 0 1 Line address 0 1 2 : 62 63 2008/12/30 26 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 3. Page Address Set Specifies page address to load display RAM data to page address register. Any RAM data bit can be accessed when its page address and column address are specified. The display remains unchanged even when the page address is changed. Page address 8 is the display RAM area dedicated to the indicator, and only D0 is valid for data change. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 1 1 A3 A2 A1 A0 Hex B0h to B8h www..com A3 0 0 0 0 1 4. A2 0 0 0 : 1 0 A1 0 0 1 1 0 A0 0 1 0 1 0 Page address 0 1 2 : 7 8 Column Address Set Specifies column address of display RAM. Divide the column address into 4 higher bits and 4 lower bits. Set each of them succession. When the microprocessor repeats to access the display RAM, the column address counter is incremental by during each access until address 132 is accessed. The page address is not changed during this time. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 Hex 10h to 18h 00h to 0Fh High nibble Low nibble A7 0 0 0 1 1 A6 0 0 0 0 0 A5 0 0 0 0 0 A4 0 0 0 : 0 0 A3 0 0 0 0 0 A2 0 0 0 0 0 A1 0 0 1 1 1 A0 0 1 0 0 1 Column address 0 1 2 : 130 131 2008/12/30 27 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 5. Read Status E R/W /RD /WR 0 1 www..com A0 0 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 BUSY /ADC OFF/ON RESET BUSY: When high, the NT75451 is busy due to internal operation or reset. Any command is rejected until BUSY goes low. The busy check is not required if enough time is provided for each cycle. /ADC: Indicates the relationship between RAM column address and segment drivers. When low, the display is reversed and column address "131-n" corresponds to segment driver n. when high, the display is normal and column address corresponds to segment driver n. OFF/ON: Indicates whether the display is on or off. When low, the display turns on. When high, the display turns off. This is the opposite of Display ON/OFF command. RESET: Indicates the initialization is in progress by /RES signal or by reset command. When low, the display is on. When high, the chip is being reset. 6. Write Display Data Write 8-bit data in display RAM. As the column address automatically increments by 1 after each write, the microprocessor can continue to write data of multiple words. A0 1 7. E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 Write Data Read Display Data Reads 8-bit data from display RAM area specified by column address and page address. As the column address automatically increments by 1 after each write, the microprocessor can continue to read data of multiple words. A single dummy read is required immediately after column address setup. Refer to the display RAM section of FUNCTIONAL DESCRIPTION for details. Note that no display data can be read via the serial interface. A0 1 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 0 1 Read Data 8. ADC Select Changes the relationship between RAM column address and segment driver. The order of segment driver output pads could be reversed by software. This allows flexible IC layout during LCD module assembly. For details, refer to the column address section of Figure 4. When display data is written or read, the column address is incremented by 1 as shown in Figure 4. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 1 0 0 0 0 0 1 Hex A0h A1h Setting Normal Reverse Ver 1.0 2008/12/30 28 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 9. Normal/ Reverse Display Reverses the Display ON/OFF status without rewriting the contents of the display data RAM. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 1 0 0 1 1 0 1 Hex A6h A7h Setting RAM Data "H" LCD ON voltage (normal) RAM Data "L" LCD ON voltage (reverse) www..com 10. Entire Display ON Forcibly turns the entire display on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This command has priority over the Normal/Reverse Display command. When D is low, the normal display status is provided. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 1 0 0 1 0 0 1 Hex A4h A5h Setting Normal display mode Display all points ON When D0 is high, the entire display ON status is provided. If the Entire Display ON command is executed in the display OFF status, the LCD panel enters Power save mode. Refer to the Power Save section for details. 11. LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 1 0 0 0 1 0 1 Hex 1/33 Duty 1/49 1/65 A2h 1/6 bias 1/8 bias 1/9 bias A3h 1/5 bias 1/6 bias 1/7 bias 12. Read-Modify-Write A pair of Read-Modify-Write and End commands must always be used. Once Read-Modify-Write is issued, column address is not incremental by Read Display Data command but incremental by Write Display Data command only. It continues until End command is issued. When the End is issued, column address returns to the address when Read-Modify-Write is issued. This can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or other events. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 1 0 0 0 0 0 Hex E0h Note: Any command except Read/Write Display Data and Column Address Set can be issued during Read-Modify-Write mode. 2008/12/30 29 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Cursor display sequence Set Page Address Set Column Address Read-Modify-Write Dummy Read Read Data No Data process www..com Write Data Completed? Yes End 13. End Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write is issued) A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 1 0 1 1 1 0 Hex EEh Return Column address N N+1 N+2 N+3 N+m N End Read-Modify-Write mode is selected 2008/12/30 30 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 14. Reset This command resets the Display Start Line register, Column Address counter, Page Address register, and Common output mode register, the V0 voltage regulator internal resistor ratio register, the Electronic Volume register, the static indicator mode register, the read-modify-write mode register, and the test mode. The Reset command does not affect on the contents of display RAM. Refer to the Reset circuit section of Function Description. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 1 0 0 0 1 0 Hex E2h www..com The Reset command cannot initialize LCD power supply. Only the Reset signal to the /RES pad can initialize the supplies. 15. Output Status Select Register When D3 is high or low, the scan direction of the COM output pad is selectable. Refer to Output Status Selector Circuit in Function Description for details. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 0 0 0 1 *: Invalid bit D3 = 0: Normal (COM0 COM63/47/31) D3 = 1: Reverse (COM63/47/31 COM0) 16. Power Control Set Select one of eight power circuit functions using 3-bit register. An external power supply and part of on-chip power circuit can be used simultaneously. Refer to Power Supply Circuit section of FUNCTIONAL DESCRIPTION for details. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 0 0 1 0 1 A2 * A0 Hex 28h to 2Fh * * * Hex C0h to C7h C8h to CFh When A0 goes low, voltage follower turns off. When A0 goes high, it turns on. When A2 goes low, voltage booster turns off. When A2 goes high, it turns on. When A2, A0 go low, both voltage booster and follower turn off, and external power is needed. 2008/12/30 31 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 17. V0 Voltage Regulator Internal Resistor Ratio Set This command sets the V0 voltage regulator internal resistor ratio. For details, see explanation under "The Power Supply Circuits". A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 : 1 1 0 1 0 1 0 Hex 20h 21h 22h : 26h 27h Large : Rb/Ra Ratio Small www..com 18. The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V0 through the output from the voltage regulator circuits of the internal liquid crystal power supply. It is a two-byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. (1) The Electronic Volume Mode Set When this command is input, the electronic volume register set command is enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 0 0 0 0 0 1 Hex 81h (2) Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal voltage V0 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 * * 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 : 1 1 0 1 1 0 Hex XX XX : XX XX Large : V0 Small When the electronic volume function is not used, set D5 - D0 to 100000. 2008/12/30 32 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 19. Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double bytes command paired with the static indicator register set command, and thus command must be executed one after the other. (The static indicator OFF command is a single byte command) (1) Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 1 0 1 1 0 0 1 Hex ACh ADh Setting Static Indicator OFF Static Indicator ON www..com (2) Static Indicator Register Set This command sets two bits of data into the static indicator register and used to set the static indicator into a blinking mode. A0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 0 1 0 * * * * * * 00 0 1 1 1 0 1 Hex XX XX XX XX OFF ON (blinking at approximately 1 second intervals) ON (blinking at approximately 0.5 second intervals) ON (constantly on) Indicator Display Status 2008/12/30 33 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 20. Power Save (Compound Command) When all displays are turned on during display off, the Power Save command is issued to greatly reduce current consumption. If the static indicator is off, the Power Save command makes the system enter sleep mode. If the static indicator is on, this command makes the system enter standby mode. Release the Sleep mode using the both Power Save OFF command (Display ON command or Entire Display OFF command) and Set Indicator On command. Static Indicator OFF Static Indicator ON www..com Power Save (Display OFF and Entire Display ON) (Sleep mode) (Standby mode) Power Save OFF (Display ON or Entire Displays OFF ) Static Indicator ON (Sleep mode released) (Standby mode released) Sleep Mode This mode stops every operation of the LCD display system, and can reduce current consumption nearly to a static current value if no access is made from the microprocessor. The internal status in the sleep mode is as follows: (1) Stops the oscillator circuit and LCD power supply circuit. (2) Stops the LCD driver and outputs the VSS level as the segment/common driver output. (3) Holds the display data and operation mode provided before the start of the sleep mode. (4) The MPU can access the built-in display data RAM. Standby Mode Stops the operation of the duty LCD displays system and turns on only the static drive system to reduce current consumption to the minimum level required for static drive. The ON operation of the static drive system indicates that the NT75451 is in standby mode. The internal status in the standby mode is as follows: (1) Stops the LCD power supply circuit. (2) Stops the LCD drive and outputs the VSS level as the segment / common driver output. However, the static drive system still operates. (3) Holds the display data and operation mode provided before the start of the standby mode. (4) The MPU can access the built-in display data RAM. When the Reset command is issued in the standby mode, the sleep mode is set. When the LCD drive voltage level is given by an external resistive driver, the current of this resistor must be cut so that it may be fixed to floating or VSS level, prior to or concurrently with causing the NT75451 to go to the sleep mode or standby mode. When an external power supply is used, likewise, the function of this external power supply must be stopped so that it may be fixed to floating or VSS level, prior to or concurrently with causing the NT75451 to go to the sleep mode or standby mode. 2008/12/30 34 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 21. NOP Non-Operation Command. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 1 0 0 0 1 1 Hex E3h www..com 22. Oscillation Frequency Select This command is to select the oscillation frequency of driver IC as below. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 1 0 0 1 0 0 1 Hex Oscillation Frequency E4h E5h Typical 31.4 KHz Typical 26.3 KHz 23. Partial Display Mode Set This command enables to select the display mode. When D0 is low, the IC is in normal display mode, the maximum display duty ratio is decided by pin connection of DUTY0 and DUTY1 and the command LCD Bias Set decides the LCD bias ratio. The IC enters into partial display mode when D0 is high, then the commands Partial Display Duty Set and Partial Display Bias Set decide the LCD display duty and bias ratios. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 0 0 0 0 1 0 1 Hex 82h 83h Display Mode Normal Display Partial Display 2008/12/30 35 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com 24. Partial Display Duty and Bias Set These two commands set the LCD display duty and bias ratios when the IC is in partial display mode. They are invalid when the IC is in normal display mode. When the partial display duty is set, the LCD bias for partial display is set simultaneous as below. The partial display duty will be kept at maximum duty (decided by pins DUTY0 and DUTY1) when setting duty is larger than maximum duty. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 * Hex 30h 31h 32h 33h 34h 35h 37h Partial Duty 1/9 duty Scanning Line Line [0:7], COMS 1/17 duty Line [0:15], COMS 1/33 duty Line [0:31], COMS 1/49 duty Line [0:47], COMS 1/65 duty Line [0:63], COMS Reserved No effect Using Partial Display Bias Set command to change the LCD bias in partial display mode. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Hex 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh LCD Bias 1/4 1/5 1/6 1/7 1/8 1/9 Reserved Reserved Note: The COM waveform of no display area is non-select waveform. 2008/12/30 36 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 25. Partial Start Line Set (Double Byte Command) This command makes it possible to set the partial start line for partial display. It is a two-byte command used as a pair and the Number of Start Line Set command must be issued after the Partial Start Line Set command. (1) Partial Start Line Set When this command is input, no other command except for the Number of Start Line Set command can be used. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 0 1 0 0 1 1 Hex D3h www..com (2) Number of Start Line Set By using this command to set six bits of data to the Partial Start Line register. Once the Number of the Start Line Set command has been used to set data into the register, then the partial start line will affect on the LCD display. The number of partial start line is always equal to zero when the partial start line is larger than maximum duty ratio (decided by pins DUTY0 and DUTY1). A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 * * 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 : 1 1 1 1 0 1 0 0 1 0 1 0 Hex XX XX XX : XX XX Partial Start Line 0 line 1 line 2 line : 62 line 63 line 2008/12/30 37 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 26. The N-Line Inversion (Double Byte Command) This command makes it possible to adjust the number of scan lines for liquid crystal display inversion. It is a two-byte command used as a pair and the Number of Line Set command must be issued after the N-Line Inversion Set command. (1) N-Line Inversion Set When this command is input, no other command except for the Number of Line Set command can be used. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 0 0 0 1 0 1 Hex 85h www..com (2) Number of Line Set By using this command to set five bits of data to the N-Line inversion register. Once the Number of Line Set command has been used to set the data into the register, then the N-Line inversion will affect on the LCD display. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 * * * 0 0 1 0 0 1 0 0 : 1 1 1 0 0 0 1 Hex XX XX : XX Line Inversion 1 line 2 line : 32 line Note 1: The number of inversed scan line = register setting value + 1. Note 2: When Partial Duty = 1/9 or 1/17, the N-line inversion function release and the LCD display scan line is back to frame inversion status. 12 3 4 5 6 m Frame Inversion N-line Inversion M n n M' 27. Release N-Line Inversion This command is used to exit the N-Line inversion function. The N-Line inversion function is released and the LCD display is set back to frame inversion status once this command is executed. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 0 0 0 0 1 0 0 Hex 84h 2008/12/30 38 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com 29. Select DC-DC Set-Up (Double Byte Command) This command makes it possible to set up the DC/DC multiple factors. By using this command to select 4 types of DC/DC multiple factors. After H/W reset, the DC-DC set-up will be the CP setting value. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 /RD /WR 1 0 1 * 0 * 0 * 0 * 1 * 0 * 0 D0 1 Hex 89h XX DC[1:0] A0 0 E R/W D7 D6 D5 D4 D3 D2 /RD /WR 1 0 * * * * * * * * * * * * * * * * * * * * * * * * DC[1:0] 0 0 1 1 0 1 0 1 Hex 00h 01h 02h 03h Select DC-DC converter circuit 5 times boosting circuit 4 times boosting circuit 3 times boosting circuit 3 times boosting circuit 30. Test Command This is the dedicated IC chip test command. It must not be used for normal operation. If the Test command is issued inadvertently, set the /RES input to low or issue the Reset command to release the test mode. A0 0 E R/W D7 D6 D5 D4 D3 D2 D1 D0 /RD /WR 1 0 1 1 1 1 0 1 0 0 Hex F0h to FFh *: Invalid bit Cautions: The NT75451 maintains an operation status specified by each command. However, the internal operation status may be changed by a high level of ambient noise. Users must consider how to suppress noise on the package and system or to prevent ambient noise insertion. To prevent a spike in noise, built-in software for periodical status refreshment is recommended. The test command can be inserted in an unexpected place. Therefore it is recommended to enter the test mode reset command F0h during the refresh sequence. 2008/12/30 39 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Table13. Command Table Command (1) Display OFF (2) Display Start Line Set A0 0 0 /RD 1 1 /WR 0 0 Code D7 1 0 D6 0 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 Hex AEh AFh 40h to 7Fh B0h to B8h www..com Function Turn on LCD panel when high, and turn off when low Specifies RAM display line for COM0 Set the display data RAM page in Page Address register Display Start Address (3) Page Address Set 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Page Address Higher Column Address Lower Column Address 0 0 0 (4) Column Address Set 0 (5) Read Status (6) Write Display Data (7) Read Display Data (8) ADC Select (9) Normal/Reverse Display (10) Entire Display ON/OFF (11) LCD Bias Set (12) Read-Modify-Write (13) End (14) Reset (15) Common Output Mode Select (16) Power Control Set (17) V0 Voltage Regulator Internal Resistor ratio Set (18) Electronic Volume mode Set Electronic Volume Register Set (19) Set Static indicator ON/OFF Set Static Indicator Register (20) Power Save (21) NOP 0 1 1 0 0 0 0 0 0 0 0 Set 4 higher bits and 4 lower bits 00h of column address of display data to RAM in register 18h XX Reads the status information XX Write data in display data RAM XX Read data from display data RAM 0 1 0 1 0 1 0 1 0 0 0 A0h A1h A6h A7h A4h A5h A2h A3h E0h Set the display data RAM address SEG output correspondence Normal indication when low, but full indication when high Select normal display (0) or entire display on Sets LCD driving voltage bias ratio Status Write Data Read Data 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 1 0 0 1 0 1 0 1 1 Increments column address counter during each write EEh Releases the Read-Modify-Write E2h Resets internal functions Select COM output scan direction *: invalid data Select the power circuit operation mode Select internal resistor ratio Rb/Ra mode 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 * 1 * 1 0 0 * 0 * 1 1 0 0 0 0 0 C0h to * * * CFh 28h Operation Status to 2Fh 20h to Resistor Ratio 27h 0 0 1 81h Electronic Control Value 1 * 1 0 * 0 1 * 0 1 * 0 0 0 1 Mode 1 1 Sets the V0 output voltage electronic volume register ACh Sets static indicator ON/OFF ADh 0: OFF, 1: ON Sets the flash mode XX XX Compound command of Display OFF and Entire Display ON E3h Command for non-operation - 2008/12/30 40 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Command Table (continue) Command (22)Oscillation Frequency Select (23)Partial Display mode Set (24)Partial Display Duty Set (25)Partial Display Bias Set (26)Partial Start Line Set Partial Start Line Set (27)N-Line Inversion Set Number of Line Set (28)N-Line Inversion Release (29)DC/DC Multiple Set A0 0 0 0 0 0 0 0 0 0 0 0 (30)Test Command (31)Test Mode Reset 0 0 /RD 1 1 1 1 1 1 1 1 1 1 1 1 1 /WR 0 0 0 0 0 0 0 0 0 0 0 0 0 Code D7 1 1 0 0 1 1 1 * 1 1 * 1 1 D6 1 0 0 0 1 1 0 * 0 0 * 1 1 0 * 0 0 * 1 1 0 0 * 1 1 D5 1 0 1 1 0 D4 0 0 1 1 1 D3 0 0 0 1 0 0 D2 1 0 D1 0 1 Duty Ratio Bias Ratio 1 1 D0 0 1 0 1 Hex www..com Function E4h Select the oscillation frequency E5h 82h Enter/Release the partial display 83h mode 30h 37h 38h 3Fh D3h XX Sets the LCD duty ratio for partial display mode Sets the LCD bias ratio for partial display mode Enter Partial Start Line Set Sets the LCD Number of partial display start line Enter N-Line inversion Sets the number of line used for N-Line inversion Exit N-Line Inversion Partial Start Line 0 0 1 0 1 85h XX Number of Line 0 1 * * 0 1 0 * * 0 0 0 0 1 84h DC[1:0] * 0 * 0 89h Select the step-up of the internal voltage converter XX F1h IC test command. Do not use! to FFh F0h Command of test mode reset Note: Do not use any other command, or system malfunction may result. 2008/12/30 41 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Command Description www..com Instruction Setup: Reference 1. Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V0 - V4) and the VDD pin, the picture on the display may instantaneously become totally dark when the power is turned on. To avoid such failure, we recommend the following flow sequence when turning on the power. 1.1. When the built-in power is being used immediately after turning on the power: 2008/12/30 42 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 1.2. When the built-in power is not being used immediately after turning on the power www..com Turn ON the VDD - VSS power keeping the /RES pin = "L" When the power is stabilized Release the reset state. (/RES pin = "H") Initialized state (Default) Power saver START (multiple commands) Function setup by command input (User setup) (11) LCD bias setting (8) ADC selection (15) Common output state selection Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V0 voltage (18) Electronic volume control Power saver OFF Function setup by command input (User setup) (16) Power control setting This concludes the initialization 2008/12/30 43 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 2. Data Display www..com End of initialization Function setup by command input (User setup) (2) Display start line set (3) Page address set (4) column address set Function setup by command input (user setup) (6) Display data write Function setup by command input (User setup) (1) Display ON/OFF End of data display 3. Power OFF Optional status Function setup by command input (User setup) (20) Power save VDD-VSS power OFF 2008/12/30 44 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Absolute Maximum Rating www..com DC Supply Voltage (VDD, VDD2, VDD3) .............................................................. -0.3V to +4.0V DC Supply Voltage (V0) ........................................................................ -0.3V to +15.0V Input Voltage (Vin) ................................................................................... -0.3V to VDD+0.3V Operating Ambient Temperature ..................................................................... -40C to +85C Storage Temperature ................................................................................. -55C to +125C *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics DC Characteristics Symbol VDD (VSS = 0V, VDD = 1.8 ~ 3.6V, Ta = -40 ~ +85C unless otherwise specified) Min. 1.8 2.4 2.6 Typ. Max. Unit 3.6 3.6 3.6 V V V 3X~ 5X boosting Condition Parameter Operating Voltage VDD3 Operating Voltage VDD2 Operating Voltage Voltage Regulator Operating Voltage V0 4.0 1.36 1.40 14.2 1.44 V V Ta = 25C, -0.05%/C VREG Reference Voltage - 20 35 VDD = 3V, V0 = 9V, built-in boosting power supply off, display on, A display data = checker and no access, Ta = 25C IDD Current Consumption -150 200 VDD, VDD2 , VDD3 = 3V, V0 = 9V, 5X built-in boosting power supply, display on, display data = checker and no access, A temperature coefficient is -0.05%/ C, Ta = 25C. 2008/12/30 45 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 DC Characteristics (continued) Symbol ISP Parameter Min. 0.8 x VDD VSS 0.8 x VDD VSS -1.0 -3.0 Typ. 0.01 Max. Unit 5 30 VDD 0.2 x VDD VDD 0.2 x VDD 1.0 3.0 Condition Sleep Mode Current Consumption Standby Mode ISB Current Consumption High-Level Input VIHC Voltage Low-Level Input VILC Voltage High-Level Output VOHC Voltage Low -Level Output VOLC Voltage ILI IHZ Input Leakage Current HZ Leakage Current LCD Driver ON Resistance www..com A During sleep, Ta = 25C A During standby, Ta = 25C V V V V A0, D0 - D7, /RD (E), /WR (R/W), /CS1, CS2, CLS, CL, FR, C86, P/S, /RES and CP IOH = -0.5mA (D0 - D7, FR, FRS and CL) IOL = 0.5mA (D0 - D7, FR, FRS and CL) RON1 - 2.0 3.5 RON2 CIN LCD Driver ON Resistance Input Pad Capacity 78.0 3.2 5.0 80.5 67.4 5.4 8.0 83.0 69.9 fFRM Frame Frequency 64.9 Vin = VDD or VSS (A0, /RD (E), /WR A (R/W), /CS1, CS2, CLS, M/S, C86, P/S and /RES) When the D0 - D7, FR and CL are in high A impedance Ta = 25C, K V0 = 11.0V These are the resistance values for when a 0.1V voltage is applied between the output terminals SEGn or COMn and the various power K V0 = 8.0V supply terminal (V0, V1, V2, V3, V4) pF Ta = 25C, f = 1MHz fOSC = 31.4 KHz, 1/65duty Hz VDD = 1.8~3.6V fOSC = 26.3 KHz, 1/65duty Hz VDD = 1.8~3.6V Notes: 1. Voltages V0 V1 V2 V3 V4 VSS2 must always be satisfied. 2. fFR=2x fFRM. 2008/12/30 46 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 AC Characteristics 1. System Buses Read/Write Characteristics (for 8080 Series MPU) www..com A0 tAS8 tAH8 /CS1 (CS2) tCYC8 tCCLW, tCCLR tCCHW, tCCHR tDS8 tDH8 /WR, /RD D0~D7 (Write) tACC8 tCH8 D0~D7 (Read) (VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85C) Symbol TAH8 TAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR TDS8 TDH8 tACC8 TCH8 Parameter Address hold time Address setup time System cycle time Control low pulse width (write) Control low pulse width (read) Control high pulse width (write) Control high pulse width (read) Data setup time Data hold time /RD access time Output disable time Min. 0 0 240 80 80 80 60 30 0 5 Typ. Max. 70 50 Unit ns ns ns ns ns ns ns ns ns ns ns /WR /RD /WR /RD D0~D7 A0 Condition D0~D7, CL = 100pF 2008/12/30 47 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 System Buses Read/Write Characteristics (for 8080 Series MPU) (continued) www..com (VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85C) Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tCH8 Parameter Address hold time Address setup time System cycle time Control low pulse width (write) Control low pulse width (read) Control high pulse width (write) Control high pulse width (read) Data setup time Data hold time /RD access time Output disable time Min. 0 0 400 150 150 120 120 80 0 10 Typ. Max. 240 100 Unit ns ns ns ns ns ns ns ns ns ns ns /WR /RD /WR /RD D0~D7 A0 Condition D0~D7, CL = 100pF *1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less. (tr + tf) < (tCYC8 - tCCLW - tCCHW) for write, (tr + tf) < (tCYC8 - tCCLR - tCCHR) for read. *2. All timing is specified using 20% and 80% of VDD as the reference. *3. tCCLW and tCCLR are specified as the overlap interval when /CS1 is low (CS2 is high) and /WR or /RD is low. 2008/12/30 48 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 2. System Buses Read/Write Characteristics (for 6800 Series MPU) www..com A0,R/W tAS6 tAH6 /CS1 (CS2) tCYC6 tEWLW, tEWLR tEWHW, tEWHR tDS6 tDH6 E D0~D7 (Write) tACC6 tOH6 D0~D7 (Read) (VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85C) Symbol tAH6 tAS6 tCYC6 tEWHW tEWHR tEWLW tEWLR tDS6 tDH6 tACC6 tOH6 Parameter Address hold time Address setup time System cycle time Control high pulse width (write) Control high pulse width (read) Control low pulse width (write) Control low pulse width (read) Data setup time Data hold time /RD access time Output disable time Min. 0 0 240 80 80 80 60 30 0 5 Typ. Max. 70 50 Unit ns ns ns ns ns ns ns ns ns ns ns E E E E D0~D7 D0~D7 CL = 100pF Condition A0, R/W 2008/12/30 49 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 System Buses Read/Write Characteristics (for 6800 Series MPU) (continued) www..com (VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85C) Symbol tAH6 tAS6 tCYC6 tEWHW tEWHR tEWLW tEWLR tDS6 tDH6 tACC6 tOH6 Parameter Address hold time Address setup time System cycle time Control high pulse width (write) Control high pulse width (read) Control low pulse width (write) Control low pulse width (read) Data setup time Data hold time /RD access time Output disable time Min. 0 0 400 150 150 120 120 80 0 10 Typ. Max. 240 100 Unit ns ns ns ns ns ns ns ns ns ns ns E E E E D0~D7 D0~D7 CL = 100pF Condition A0, R/W *1. The input signal rise time and fall time (tr, tf) is specified at 15ns or less. (tr + tf) < (tCYC6 - tEWLW - tEWHW) for write, (tr + tf) < (tCYC6 - tEWLR - tEWHR) for read. *2. All timing is specified using 20% and 80% of VDD as the reference. *3. tEWHW and tEWHR are specified as the overlap interval when /CS1 is low (CS2 is high) and E is high. 2008/12/30 50 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 3. Serial Interface Timing tCSS tSCYC tCSH www..com /CS1 (CS2) tr tSHW tSLW SCL tf tSAS tSAH A0 tSDS tSDH SI (VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85C) Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Parameter Serial clock cycle Serial clock H pulse width Serial clock L pulse width Address setup time Address hold time Data setup time Data hold time Chip select setup time Chip select hold time Min. 100 50 50 30 20 30 20 30 60 Typ. Max. Unit ns ns ns ns ns ns ns ns ns SCL SCL SCL A0 A0 SI SI /CS1, CS2 /CS1, CS2 Condition 2008/12/30 51 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Serial Interface Timing (continued) www..com (VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85C) Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS Parameter Serial clock cycle Serial clock H pulse width Serial clock L pulse width Address setup time Address hold time Data setup time Data hold time Chip select setup time Min. 200 80 80 60 30 60 30 40 Typ. Max. Unit ns ns ns ns ns ns ns ns SCL SCL SCL A0 A0 SI SI /CS1, CS2 /CS1, CS2 Condition tCSH Chip select hold time 100 ns *1. The input signal rise time and fall time (tr, tf) is specified as 15ns or less. *2. All timing is specified using 20% and 80% of VDD as the standard. 2008/12/30 52 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 4. Display Control Timing www..com CL (Output) tDFR FR (VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85C) Symbol tDFR Parameter FR delay time Min. Typ. 20 Max. 80 Unit ns CL = 50 pF (VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85C) Symbol tDFR Parameter FR delay time Min. Typ. 40 Max. 160 Unit ns CL = 50 pF Condition Condition 5. Reset Timing tRW tR /RES Internal Status During Reset (VDD = 2.7 ~ 3.6V, Ta = -40 ~ +85C) Symbol tR tRW Parameter Reset Time Reset low pulse width Min. 10 Typ. Max. 1.0 Unit s s /RES Condition (VDD = 1.8 ~ 2.7V, Ta = -40 ~ +85C) Symbol tR tRW Parameter Reset Time Reset low pulse width Min. 20 Typ. Max. 2.0 Unit s s /RES Condition 2008/12/30 53 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Microprocessor Interface (for reference only) 8080-series microprocessors V DD www..com V CC A0 A1 to A7 /IORQ A0 V DD Decoder /CS1 CS2 C86 MPU D0 to D7 /RD /WR /RES GND D0 to D7 /RD /WR NT75451 V SS V DD P/S /RES V SS V SS Figure 9 6800-series microprocessors Figure 10 2008/12/30 54 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Application information for LCD panel (for reference only) www..com 1. Type I (ADC Select = 0, COM Output Select = 1) CC C OO O MM M 0S 1 0 COM11 COM12 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 SS EE GG 91 0 S E G 1 2 7 S E G 1 2 8 S E G 1 2 9 S E G 1 3 0 S E G 1 3 1 C CC OO O MM M 4 33 23 3 COM44 COM45 COM31 IC Bumper Face Down COM63 COMS 2. Type II (ADC Select = 1, COM Output Select = 0) COMS COM63 COM45 COM44 CC C OO O MM M 33 4 3 32 S E G 1 3 1 S E G 1 3 0 S E G 1 2 9 S E G 1 2 8 S E G 1 2 7 S E G 1 2 6 S E G 1 2 5 S E G 1 2 4 S E G 1 2 3 S E G 1 2 2 IC Bumper Face Down S E G 4 S E G 3 S E G 2 S E G 1 S E G 0 COM31 COM12 COM11 C CC O OO M MM 1 S0 0 2008/12/30 55 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com 3. Type III (ADC Select = 1, COM Output Select = 1) CC C OO O MM M 33 4 3 32 COM44 COM45 COM63 COMS S E G 1 3 1 S E G 1 3 0 S E G 1 2 9 S E G 1 2 8 S E G 1 2 7 S E G 1 2 6 S E G 1 2 5 S E G 1 2 4 S E G 1 2 3 SS EE GG 11 22 21 S E G 4 S E G 3 S E G 2 S E G 1 S E G 0 CC OO MM S0 IC Bumper Face Up C O M 1 0 COM11 COM12 COM31 4. Type IV (ADC Select = 0, COM Output Select = 0) COM31 COM12 COM11 C CC O OO M MM 1 0S 0 IC Bumper Face Up S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 S E G 5 S E G 6 S E G 7 S E G 8 S E G 9 S E G 1 2 7 S E G 1 2 8 S E G 1 2 9 S E G 1 3 0 S E G 1 3 1 COMS COM63 COM45 COM44 C CC O OO MM M 4 33 23 3 2008/12/30 56 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 www..com Application information for Pin Connection to MPU (for reference only) 1. 8080 MPU Mode: (DUTY0,1 = 11: 1/65duty, CP= 0 : 4x , CLS = 1: Internal display OSC) COM63 COMS FRS FR OTP_PWR CL CP VSS_OPT /CS1 CS2 /RES A0 /WR /RD D0 D1 D2 D3 D4 D5 D6 D7 DUTY0 DUTY1 VDD VDD3 VDD2 COM34 COM33 COM32 SEG131 SEG130 SEG129 SEG128 SEG127 COM48 COM49 COM47 COM46 OTP_PWR /CS1 /RES A0 /WR /RD D[0..7] VDD VSS VSS VSS3 VSS2 V1 V2 V3 V4 V0 SEG4 SEG3 SEG2 SEG1 SEG0 COMS COM0 COM1 C1 CLS C86 P/S VSS COM15 COM16 COM30 COM31 COM13 COM14 2008/12/30 57 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 2. www..com 6800 MPU Mode: (DUTY0,1 = 11: 1/65duty, CP = 0 : 4x, CLS = 1: Internal display OSC.) FRS FR OTP_PWR OTP_PWR CL CP VSS_OPT /CS1 /RES A0 R/W E D[0..7] /CS1 CS2 /RES A0 /WR /RD D0 D1 D2 D3 D4 D5 D6 D7 DUTY0 DUTY1 VDD VDD3 VDD2 COM34 COM33 COM32 SEG131 SEG130 SEG129 SEG128 SEG127 COM63 COMS COM48 COM49 COM47 COM46 VDD VSS VSS VSS3 VSS2 V1 V2 V3 V4 V0 C1 SEG4 SEG3 SEG2 SEG1 SEG0 COMS COM0 COM1 COM2 CLS C86 VSS P/S COM15 COM16 COM30 COM31 COM13 COM14 2008/12/30 58 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 3. Serial Mode: (DUTY0,1 = 11: 1/65duty, CP = 0 : 4x, CLS = 1: Internal display OSC.) www..com COM63 COM48 COM49 COMS FRS FR OTP_ PWR OTP_ PWR CL CP /CS1 / RES A0 VSS_ OPT /CS1 CS2 / RES A0 /WR /RD D0 D1 D2 D3 D4 D5 D6 D7 DUTY0 DUTY1 VDD VDD VDD3 VDD2 COM34 COM33 COM32 SEG131 SEG130 SEG129 SEG128 SEG127 COM47 COM46 SCL SI VSS VSS VSS3 VSS2 V1 V2 V3 V4 V0 SEG4 SEG3 SEG2 SEG1 SEG0 COMS COM0 COM1 COM2 C1 CLS C86 P/S VSS COM15 COM16 COM30 COM31 COM13 COM14 2008/12/30 59 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Bonding Diagram www..com Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 2008/12/30 Designation FRS FR OTP_PWR OTP_PWR CL CP VSS_OPT /CS1 CS2 /RES A0 /WR /RD VDD_OPT D0 D1 D2 D3 D4 D5 D6 D7 DUTY0 VSS_OPT DUTY1 VDD VDD VDD VDD3 X -2080.5 -2007.5 -1934.5 -1861.5 -1788.5 -1715.5 -1642.5 -1569.5 -1496.5 -1423.5 -1350.5 -1277.5 -1204.5 -1131.5 -1058.5 -985.5 -912.5 -839.5 -766.5 -693.5 -620.5 -547.5 -474.5 -401.5 -328.5 -255.5 -182.5 -109.5 -36.5 Y -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 60 Pad No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Designation VDD3 VDD3 VDD2 VDD2 VDD2 VDD2 VSS VSS VSS VSS3 VSS3 VSS3 VSS2 VSS2 VSS2 VSS2 V1 V2 V3 V4 V0 V0 V0 V0 VDD_OPT CLS C86 VSS_OPT P/S X 36.5 109.5 182.5 255.5 328.5 401.5 474.5 547.5 620.5 693.5 766.5 839.5 912.5 985.5 1058.5 1131.5 1204.5 1277.5 1350.5 1423.5 1496.5 1569.5 1642.5 1715.5 1788.5 1861.5 1934.5 2007.5 2080.5 Y -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 -297.5 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Pad No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 2008/12/30 Designation COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS SEG0 SEG1 SEG2 X 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2375 2389.5 2360.5 2331.5 2302.5 2273.5 2244.5 2215.5 2186.5 2157.5 2128.5 2099.5 2070.5 2041.5 2012.5 1983.5 1954.5 1899.5 1870.5 1841.5 Y -298.65 -269.65 -240.65 -211.65 -182.65 -153.65 -124.65 -95.65 -66.65 -37.65 -8.65 20.35 49.35 78.35 107.35 136.35 165.35 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 Pad No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 61 Designation SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 X www..com Y 1812.5 262 1783.5 1754.5 1725.5 1696.5 1667.5 1638.5 1609.5 1580.5 1551.5 1522.5 1493.5 1464.5 1435.5 1406.5 1377.5 1348.5 1319.5 1290.5 1261.5 1232.5 1203.5 1174.5 1145.5 1116.5 1087.5 1058.5 1029.5 1000.5 971.5 942.5 913.5 884.5 855.5 826.5 797.5 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Pad No. 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 2008/12/30 Designation SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 X 768.5 739.5 710.5 681.5 652.5 623.5 594.5 565.5 536.5 507.5 478.5 449.5 420.5 391.5 362.5 333.5 304.5 275.5 246.5 217.5 188.5 159.5 130.5 101.5 72.5 43.5 14.5 -14.5 -43.5 -72.5 -101.5 -130.5 -159.5 -188.5 -217.5 -246.5 Y 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 62 Pad No. 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 Designation SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 X www..com Y -275.5 262 -304.5 -333.5 -362.5 -391.5 -420.5 -449.5 -478.5 -507.5 -536.5 -565.5 -594.5 -623.5 -652.5 -681.5 -710.5 -739.5 -768.5 -797.5 -826.5 -855.5 -884.5 -913.5 -942.5 -971.5 -1000.5 -1029.5 -1058.5 -1087.5 -1116.5 -1145.5 -1174.5 -1203.5 -1232.5 -1261.5 -1290.5 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Pad No. 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 Designation SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM32 COM33 COM34 COM35 COM36 COM37 X -1319.5 -1348.5 -1377.5 -1406.5 -1435.5 -1464.5 -1493.5 -1522.5 -1551.5 -1580.5 -1609.5 -1638.5 -1667.5 -1696.5 -1725.5 -1754.5 -1783.5 -1812.5 -1841.5 -1870.5 -1899.5 -1954.5 -1983.5 -2012.5 -2041.5 -2070.5 -2099.5 Y 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 262 Pad No. 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 Designation COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS X www..com Y -2128.5 262 -2157.5 -2186.5 -2215.5 -2244.5 -2273.5 -2302.5 -2331.5 -2360.5 -2389.5 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 -2375 262 262 262 262 262 262 262 262 262 165.35 136.35 107.35 78.35 49.35 20.35 -8.65 -37.65 -66.65 -95.65 -124.65 -153.65 -182.65 -211.65 -240.65 -269.65 -298.65 2008/12/30 63 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Alignment Mark Location (Total: 2 pins) NO L R X Y www..com -2242 -279 2242 -279 Left side Right side (Unit: um) 2008/12/30 64 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Package Information www..com Pad Dimensions Item Chip size Chip thickness Pad No. X 1~58 59~75,76~91 4974 Size Y 748 525 73 Unit m m Pad pitch 92~223 224~239,240~256 91~92,223~224 76~91,224~239 Output Pad 92~223 59~75 240~256 Input Pad 1~58 All pads 17 106 58 29 m 55 106 17 35 15 3 m m Bump size Bump height 2008/12/30 65 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Application Notice 1. 2. 3. 4. 5. 6. 7. www..com 8. Power: VDD & VDD2 & VDD3 3.6V; VOUT & V0 15V. VDD & VDD3 must be connected together. Keep the relationship of LCD driving voltage: V0 > V1 > V2 > V3 > V4 > VSS2. Use VDD (pad 26 ~28), VDD3 (pad 29~31) and VDD2 (pad 32 ~ 35) for power supply input, and don't use VDD (pad 8, 13, 79, 87) output for pad option to power supply input pad. Use VSS (pad 36 ~ 38), VSS3 (pad 39~41) and VSS2 (pad 42 ~ 45) for ground input, and don't use VSS (pad 5, 31, 83) output for pad option to ground input pad. The reset pin of NT75451 is floating inside the IC. Please make sure the reset pin of the customer's system a fixed status ("H" or "L") while operating this pin. If using serial mode, please make sure D0~D5, /RD, /WR and C86 pads must be fixed "H" or "L". How to avoid light display when heavy loading display: a. Use heavy loading pattern (Checker or H-Bar) and measure the voltage of VOUT and V0. b. VOUT voltage should be larger than V0 about 0.5V. c. If VOUT - V0 0.5, please increase multiple of booster or VDD2 voltage. VOUT voltage should be less than 15V. You can use Oscillation Frequency Select command to adjust the frame frequency to avoid fluorescent light flickering. 2008/12/30 66 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 ITO Layout Notice www..com Specifically with COG application, it is important to reduce the resistance of ITO path. To make the overall display performance of the LCM better, there are some suggestions for ITO layout described as below: a) To reduce the effect of power noise and get better display optical performance, please separate the ITO layout of power pads (VDD, VDD2 , VDD3 & VSS, VSS2 , VSS3) outside of the LCD glass and connect them on the edge of the glass. b) Please keep the resistance of VDD , VDD2, VDD3 & VSS, VSS2 , VSS3 path 50. This value includes the ITO resistors values, the FPC/Heat seal resistor; the ACF contact resistors between IC and Glass, Glass and FPC/Heat seal, FPC/Heat seal and PCB. c) Large resistance will reduce the efficiency of voltage booster; user should make the ITO resistance of charge pump pads as small as possible. The resistance of VLCD(V0) 50. d) The value of the other pins of the interface 200 (except /RES pin). e) Make a long thin ITO line with impedance more than 4K between RESET of interface and IC's /RES pads to work as a low-pass filter. After experience, it can filter some EMI and prevent the errors caused by ESD. ITO Path Max. Resistance VDD, VDD2, VDD3, VSS, VSS2, 50 VSS3 VLCD(V0) 50 /RES 4K~10K A0, D0~D7, /CS1, /WR,/RD, C86, P/S <500 To meet the value demanded above while laying out ITO, users may accept the rules below: a) In order to keep the ITO resistance to a minimum, the vary pitch and position of the module connection to the outside should be selected to make the power lines go as straight as possible. b) The distance between NT75451 and FPC is the shorter the better. Then the length of ITO will be the shortest and you can get a smaller resistor value. c) The ITO interface may fill a blank area on the LCD Panel to reduce the ITO resistance. In order to ensure the display quality, the ITO trace for VDD and VDD2,3 should be separated. Capacitors (1uF ~ 2.2uF) connected with V0. The voltage rating of capacitor connected to V0 has to be more than 16V, Item Capacitance Max. Rating V0 1uF~2.2uF 16V 2008/12/30 67 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. NT75451 Cautions www..com 1. The contents of this document will be subjected to change without notice. 2. Precautions against light projection: Light has the effect of causing the electrons of semiconductor to move; so light projection may change the characteristics of semiconductor devices. For this reason, it is necessary to take account of effective protection measures for the packages (such as COB and COG, etc.) causing chip to be exposed to a light environment in order to isolate the projection of light on any part of the chip, including top, bottom and the area around the chip. Observe the following instructions in using this product: a. During the design stage, it is necessary to notice and confirm the light sensitivity and preventive measures for using IC on substrate (PCB, Glass or Film) or product. b. Test and inspect the product under an environment free of light source penetration. c. Confirm that all surfaces around the IC will not be exposed to light source. 2008/12/30 68 Ver 1.0 With respect to the information represented in this document, Novatek makes no warranty, expressed or implied, including the warranties of merchantability, fitness for a particular purpose, non-infringement, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any such information. |
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